Structure-based deadlock checking of asynchronous circuits

DOI10.1007/s11390-011-1199-3zbMath1280.68125MaRDI QIDQ2637261

Zhiying Wang, Hong-Guang Ren, Doug Edwards

Publication date: 11 February 2014

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11390-011-1199-3

zbMATH Keywords

verification; data-driven; deadlock; asynchronous pipeline

Mathematics Subject Classification ID

68Q60: Specification and verification (program logics, model checking, etc.)

68Q85: Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.)

Uses Software

• Punf
• CESAR