Structure-based deadlock checking of asynchronous circuits

DOI10.1007/S11390-011-1199-3MaRDI QIDQ2637261zbMATH OpenOpenAlexFDO

Authors Hong-Guang Ren, Zhiying Wang, Doug Edwards

Publication date 11 February 2014

Published in Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11390-011-1199-3

zbMATH Keywords

asynchronous pipelinedata-drivendeadlockverification

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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Cites work

• A technique of state space search based on unfolding
• A Theory of Asynchronous Control Networks
• Balsa: An Asynchronous Hardware Synthesis Language
• Enumeration of the Elementary Circuits of a Directed Graph
• Graph-Based Algorithms for Boolean Function Manipulation
• Handshake Circuits
• scientific article; zbMATH DE number 3870578 (Why is no real title available?)
• scientific article; zbMATH DE number 3757688 (Why is no real title available?)
• scientific article; zbMATH DE number 1759626 (Why is no real title available?)

Cited in

(2)

• A specification structure for deadlock-freedom of synchronous processes
• Verification of building blocks for asynchronous circuits

Describes a project that uses

Uses Software

• Punf
• CESAR

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