scientific article; zbMATH DE number 3861073

MaRDI QIDQ3329397zbMATHFDO

Authors Bud Mishra, Edmund Clarke

Publication date 1984

zbMATH Keywords

asynchronous circuitautomatic verificationmodel checkerspecifications for circuits in a branching time temporal logic

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15) Abstract data types; algebraic specification (68Q65) Theory of operating systems (68N25)

Recommendations

• Hierarchical verification of asynchronous circuits using temporal logic
• Automatic Verification of Sequential Circuits Using Temporal Logic
• An exercise in the automatic verification of asynchronous designs
• Verification of asynchronous circuits using timed automata
• On process-algebraic verification of asynchronous circuits

Cited in

(21)

• scientific article; zbMATH DE number 139802 (Why is no real title available?)
• A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol
• Verification of asynchronous circuits using timed automata
• Towards a unifying CSP approach to hierarchical verification of asynchronous hardware
• Structure-based deadlock checking of asynchronous circuits
• Hierarchical verification of asynchronous circuits using temporal logic
• CTL\(^*\) and ECTL\(^*\) as fragments of the modal \(\mu\)-calculus
• scientific article; zbMATH DE number 4174373 (Why is no real title available?)
• An exercise in the automatic verification of asynchronous designs
• scientific article; zbMATH DE number 1953116 (Why is no real title available?)
• scientific article; zbMATH DE number 177508 (Why is no real title available?)
• scientific article; zbMATH DE number 1852152 (Why is no real title available?)
• scientific article; zbMATH DE number 4049572 (Why is no real title available?)
• scientific article; zbMATH DE number 139979 (Why is no real title available?)
• scientific article; zbMATH DE number 1955911 (Why is no real title available?)
• Automatic Verification of Sequential Circuits Using Temporal Logic
• Verification of asynchronous circuits by BDD-based model checking of Petri nets
• Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
• On process-algebraic verification of asynchronous circuits
• Automated temporal reasoning about reactive systems
• Verification of building blocks for asynchronous circuits

This page was built for publication:

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3329397)