scientific article; zbMATH DE number 3861073

zbMATH Open0541.94038MaRDI QIDQ3329397FDOQ3329397

Authors: Bud Mishra, Edmund Clarke 

Publication date: 1984

Title of this publication is not available (Why is that?)

Recommendations

• Hierarchical verification of asynchronous circuits using temporal logic
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zbMATH Keywords

asynchronous circuitautomatic verificationmodel checkerspecifications for circuits in a branching time temporal logic

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15) Abstract data types; algebraic specification (68Q65) Theory of operating systems (68N25)

Cited In (16)

• Automated temporal reasoning about reactive systems
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• Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
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• A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol
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• CTL\(^*\) and ECTL\(^*\) as fragments of the modal \(\mu\)-calculus
• An exercise in the automatic verification of asynchronous designs
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• On process-algebraic verification of asynchronous circuits
• Automatic Verification of Sequential Circuits Using Temporal Logic
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• Hierarchical verification of asynchronous circuits using temporal logic

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