Verification of bounded delay asynchronous circuits with timed traces

DOI10.1007/3-540-49253-4_7MaRDI QIDQ4250360zbMATH OpenFDO

Authors Tomohiro Yoneda, Bin Zhou, Holger Schlingloff, Bin Zhou

Publication date 1 February 2000

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-49253-4_7

zbMATH Keywords

bounded delay asynchronous circuitscomputer aided verificationexplicit state-exploration algorithmimplementationtime Petri netstrace theory

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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