RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking

DOI10.1016/S0167-9260(97)00023-0MaRDI QIDQ3840911zbMATH OpenOpenAlexFDO

Authors Vida Vakilotojar, Peter A. Beerel

Publication date 13 August 1998

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-9260(97)00023-0

zbMATH Keywords

asynchronous circuitsregister transfer level verificationsymbolic model checkingtime discretizationtiming assumptions

Mathematics Subject Classification ID

Computer system organization (68M99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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