On process-algebraic verification of asynchronous circuits
From MaRDI portal
Recommendations
Cited in
(15)- On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
- Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
- Structure-based deadlock checking of asynchronous circuits
- Using transition systems to describe and predict the behaviour of structured excitable media
- scientific article; zbMATH DE number 1670834 (Why is no real title available?)
- Towards a unifying CSP approach to hierarchical verification of asynchronous hardware
- scientific article; zbMATH DE number 3861073 (Why is no real title available?)
- scientific article; zbMATH DE number 4049572 (Why is no real title available?)
- scientific article; zbMATH DE number 139979 (Why is no real title available?)
- scientific article; zbMATH DE number 1303725 (Why is no real title available?)
- Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits
- scientific article; zbMATH DE number 1421020 (Why is no real title available?)
- scientific article; zbMATH DE number 5042670 (Why is no real title available?)
- Chemical reaction network designs for asynchronous logic circuits
- Verification of building blocks for asynchronous circuits
This page was built for publication: On process-algebraic verification of asynchronous circuits
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5431924)