Efficient verification algorithms for one-counter processes
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Computational difficulty of problems (lower bounds, completeness, difficulty of approximation, etc.) (68Q17) Analysis of algorithms and problem complexity (68Q25) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)
Recommendations
- On process-algebraic verification of asynchronous circuits
- scientific article; zbMATH DE number 5286871
- scientific article; zbMATH DE number 3958712
- The complexity of bisimilarity-checking for one-counter processes.
- One-counter verifiers for decidable languages
- Tools and Algorithms for the Construction and Analysis of Systems
- Simple and efficient batch verification techniques for verifiable delay functions
- Verified compilation of communicating processes into clocked circuits
- Verifying the correctness of parallel logical control algorithms
- Branching-time model checking of one-counter processes
Cited in
(8)- The complexity of bisimilarity-checking for one-counter processes.
- DP lower bounds for equivalence-checking and model-checking of one-counter automata
- Reachability in Succinct and Parametric One-Counter Automata
- Bisimilarity of one-counter processes is PSPACE-complete
- Model Checking FO(R) over One-Counter Processes and beyond
- Equivalence-checking with one-counter automata: A generic method for proving lower bounds
- Countdown games, and simulation on (succinct) one-counter nets
- Weak bisimilarity between finite-state systems and BPA or normed BPP is decidable in polynomial time
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