SAT-based verification for timed component connectors

DOI10.1016/J.SCICO.2011.02.003MaRDI QIDQ433331zbMATH OpenOpenAlexFDO

Authors Stephanie Kemper

Publication date 13 July 2012

Published in Science of Computer Programming (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.scico.2011.02.003

zbMATH Keywords

model checkingSATabstraction refinementcomponent-based software engineeringtimed constraint automata

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30) Specification and verification (program logics, model checking, etc.) (68Q60)

Recommendations

• SAT-based verification for timed component connectors
• Verification of timed automata via satisfiability checking
• scientific article; zbMATH DE number 1955911
• Formal Modeling and Analysis of Timed Systems
• Verification of asynchronous circuits using timed automata
• Using Coq for formal modeling and verification of timed connectors
• Formal Methods for Hardware Verification
• scientific article; zbMATH DE number 2064232

Cites work

• scientific article; zbMATH DE number 1670775 (Why is no real title available?)
• scientific article; zbMATH DE number 4022620 (Why is no real title available?)
• scientific article; zbMATH DE number 3776834 (Why is no real title available?)
• scientific article; zbMATH DE number 42752 (Why is no real title available?)
• scientific article; zbMATH DE number 176736 (Why is no real title available?)
• scientific article; zbMATH DE number 1973987 (Why is no real title available?)
• scientific article; zbMATH DE number 2102690 (Why is no real title available?)
• scientific article; zbMATH DE number 1412988 (Why is no real title available?)
• A brief history of process algebra
• A timed model for communicating sequential processes
• Abstractions from proofs
• Bounded model checking using satisfiability solving
• Calculi for synchrony and asynchrony
• Computer Aided Verification
• Modeling component connectors in Reo by constraint automata
• Process algebra with timing
• Reo: a channel-based coordination model for component composition
• SAT-based verification for timed component connectors
• Tools and Algorithms for the Construction and Analysis of Systems

Cited in

(4)

• SAT-based verification for timed component connectors
• Linear templates of ACTL formulas with an application to SAT-based verification
• Using Coq for formal modeling and verification of timed connectors
• Formal Verification for Components and Connectors

Describes a project that uses

Uses Software

• Reo
• Chaff
• FOCI
• Esterel

This page was built for publication: SAT-based verification for timed component connectors

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q433331)