Verification of timed automata via satisfiability checking
From MaRDI portal
Recommendations
Cited in
(50)- Decidable verification for reducible timed automata specified in a first order logic with time
- Presburger liveness verification of discrete timed automata.
- Fault localization of timed automata using maximum satisfiability
- Decidable \({\exists}^*{\forall}^*\) first-order fragments of linear rational arithmetic with uninterpreted predicates
- Preface to the special issue ``SI: satisfiability modulo theories
- A tool for deciding the satisfiability of continuous-time metric temporal logic
- General lower bounds and improved algorithms for infinite-domain CSPs
- On improving backwards verification of timed automata (extended abstract)
- Incremental Language Inclusion Checking for Networks of Timed Automata
- Bounded model checking for timed automata
- Bounded model checking with parametric data structures
- SAT modulo graphs: acyclicity
- SAT-based verification for timed component connectors
- Well (and better) quasi-ordered transition systems
- scientific article; zbMATH DE number 1799517 (Why is no real title available?)
- Exact Incremental Analysis of Timed Automata with an SMT-Solver
- Parametric Deadlock-Freeness Checking Timed Automata
- Time-Bounded Verification
- Verification for Timed Automata extended with Unbounded Discrete Data Structures
- Hypervolume Approximation in Timed Automata Model Checking
- From timed automata to logic -- and back
- Improvements for the Symbolic Verification of Timed Automata
- Removing all silent transitions from timed automata
- scientific article; zbMATH DE number 177500 (Why is no real title available?)
- Solving parity games by a reduction to SAT
- SAT-based verification for timed component connectors
- scientific article; zbMATH DE number 1954132 (Why is no real title available?)
- scientific article; zbMATH DE number 1956587 (Why is no real title available?)
- scientific article; zbMATH DE number 1973987 (Why is no real title available?)
- scientific article; zbMATH DE number 2064232 (Why is no real title available?)
- scientific article; zbMATH DE number 1796133 (Why is no real title available?)
- SMT-based induction methods for timed systems
- scientific article; zbMATH DE number 2104641 (Why is no real title available?)
- scientific article; zbMATH DE number 1444724 (Why is no real title available?)
- Verified certification of reachability checking for timed automata
- One More Decidable Class of Finitely Ground Programs
- Automated verification and refinement for physical-layer protocols
- SAT-based reachability checking for timed automata with discrete data
- Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
- scientific article; zbMATH DE number 5024617 (Why is no real title available?)
- scientific article; zbMATH DE number 5033900 (Why is no real title available?)
- The Power of Proofs: New Algorithms for Timed Automata Model Checking
- Theoretical Aspects of Computing - ICTAC 2004
- Unbounded, fully symbolic model checking of timed automata using Boolean methods.
- Perspectives of System Informatics
- Proving sequential function chart programs using timed automata
- Verification Modulo theories
- Abstractions for the local-time semantics of timed automata: a foundation for partial-order methods
- Algorithms and complexity of difference logic
- Verification of continuous dynamical systems by timed automata
This page was built for publication: Verification of timed automata via satisfiability checking
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5392293)
