scientific article; zbMATH DE number 1955911

MaRDI QIDQ4417609zbMATH OpenFDO

Authors Jesper Møller, Henrik Hulgaard, Henrik Reif Andersen

Publication date 29 July 2003

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2549/25490274.htm

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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• Timed verification of the generic architecture of a memory circuit using parametric timed automata
• Hierarchical verification of asynchronous circuits using temporal logic
• Timing conditions for linearizability in uniform counting networks
• Verification of asynchronous circuits using timed automata
• Consistency and satisfiability of waveform timing specifications
• Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
• Hazard checking of timed asynchronous circuits revisited
• RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
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• SAT-based verification for timed component connectors
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• Formal Methods for Components and Objects
• Automated Technology for Verification and Analysis
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• Formal Modeling and Analysis of Timed Systems
• Perspectives of System Informatics
• On specifications and proofs of timed circuits

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