Fully connected PLL networks: how filter determines the number of nodes (Q1036309): Difference between revisions

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Property / cites work: Linear approach for synchronous state stability in fully connected PLL networks / rank
 
Normal rank
Property / cites work
 
Property / cites work: All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus / rank
 
Normal rank
Property / cites work
 
Property / cites work: Nonlinear oscillations, dynamical systems, and bifurcations of vector fields / rank
 
Normal rank
Property / cites work
 
Property / cites work: Models for master-slave clock distribution networks with third-order phase-locked loops / rank
 
Normal rank
Property / cites work
 
Property / cites work: Multiple synchronous states in static delay-free mutually connected PLL networks / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q3902876 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4003780 / rank
 
Normal rank

Latest revision as of 04:35, 2 July 2024

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Fully connected PLL networks: how filter determines the number of nodes
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    Fully connected PLL networks: how filter determines the number of nodes (English)
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    13 November 2009
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    Summary: Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase-locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first-order lag-lead low-pass or when the node filters are second-order low-pass. For first- order filters, the synchronous state of the network shows to be stable for any number of nodes. For second-order filter, there is a superior limit for the number of nodes, depending on the PLL parameters.
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