FPGA based high performance double-precision matrix multiplication (Q987759): Difference between revisions
From MaRDI portal
Changed an Item |
ReferenceBot (talk | contribs) Changed an Item |
||
| (2 intermediate revisions by 2 users not shown) | |||
| Property / MaRDI profile type | |||
| Property / MaRDI profile type: MaRDI publication profile / rank | |||
Normal rank | |||
| Property / full work available at URL | |||
| Property / full work available at URL: https://doi.org/10.1007/s10766-010-0131-8 / rank | |||
Normal rank | |||
| Property / OpenAlex ID | |||
| Property / OpenAlex ID: W4249774071 / rank | |||
Normal rank | |||
| Property / cites work | |||
| Property / cites work: FPGA based high performance double-precision matrix multiplication / rank | |||
Normal rank | |||
Latest revision as of 02:48, 3 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | FPGA based high performance double-precision matrix multiplication |
scientific article |
Statements
FPGA based high performance double-precision matrix multiplication (English)
0 references
13 August 2010
0 references
high performance computing
0 references
matrix multiplication
0 references
rank-1 scheme
0 references
FPGA implementation
0 references
memory-bandwidth trade-off
0 references
scalability
0 references
