Analog property checkers: a DDR2 case study (Q5962118): Difference between revisions

@@ Property / OpenAlex ID @@
+W2084777069
@@ Property / OpenAlex ID: W2084777069 / rank @@
+Normal rank
@@ Property / cites work @@
+Q2754115
@@ Property / cites work: Q2754115 / rank @@
+Normal rank
@@ Property / cites work @@
+Q4938622
@@ Property / cites work: Q4938622 / rank @@
+Normal rank
@@ Property / cites work @@
+The benefits of relaxing punctuality
@@ Property / cites work: The benefits of relaxing punctuality / rank @@
+Normal rank
@@ Property / cites work @@
+Q2753772
@@ Property / cites work: Q2753772 / rank @@
+Normal rank
@@ Property / cites work @@
+Temporal Logic Verification Using Simulation
@@ Property / cites work: Temporal Logic Verification Using Simulation / rank @@
+Normal rank
@@ Property / cites work @@
+Q4551134
@@ Property / cites work: Q4551134 / rank @@
+Normal rank
@@ Property / cites work @@
+Q4804911
@@ Property / cites work: Q4804911 / rank @@
+Normal rank
@@ Property / cites work @@
+Automated Technology for Verification and Analysis
+Normal rank
@@ Property / cites work @@
+Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
+Normal rank
@@ Property / cites work @@
+Q4873991
@@ Property / cites work: Q4873991 / rank @@
+Normal rank
@@ Property / cites work @@
+Checking Temporal Properties of Discrete, Timed and Continuous Behaviors
+Normal rank
@@ Property / cites work @@
+Test Coverage for Continuous and Hybrid Systems
@@ Property / cites work: Test Coverage for Continuous and Hybrid Systems / rank @@
+Normal rank
@@ Property / cites work @@
+Q2754087
@@ Property / cites work: Q2754087 / rank @@
+Normal rank