Expressiveness of verifiable hierarchical clock systems (Q3005130): Difference between revisions

From MaRDI portal
Changed an Item
ReferenceBot (talk | contribs)
Changed an Item
 
(2 intermediate revisions by 2 users not shown)
Property / MaRDI profile type
 
Property / MaRDI profile type: MaRDI publication profile / rank
 
Normal rank
Property / full work available at URL
 
Property / full work available at URL: https://doi.org/10.1080/03081070701794876 / rank
 
Normal rank
Property / OpenAlex ID
 
Property / OpenAlex ID: W2103499994 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Model-checking in dense real-time / rank
 
Normal rank
Property / cites work
 
Property / cites work: A theory of timed automata / rank
 
Normal rank
Property / cites work
 
Property / cites work: Discrete Event Simulation of Hybrid Systems / rank
 
Normal rank
Property / cites work
 
Property / cites work: SYSTEM THEORETIC FORMALISMS FOR COMBINED DISCRETE-CONTINUOUS SYSTEM SIMULATION / rank
 
Normal rank
Property / cites work
 
Property / cites work: An environment for DEVS-based multiformalism simulation in common lisp/CLOS / rank
 
Normal rank
Property / cites work
 
Property / cites work: Analysis of timed systems using time-abstracting bisimulations / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4220896 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q4122858 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q3681970 / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q3996495 / rank
 
Normal rank

Latest revision as of 03:55, 4 July 2024

scientific article
Language Label Description Also known as
English
Expressiveness of verifiable hierarchical clock systems
scientific article

    Statements

    Expressiveness of verifiable hierarchical clock systems (English)
    0 references
    0 references
    0 references
    7 June 2011
    0 references
    general dynamical system
    0 references
    hierarchical I/O clock system
    0 references
    DEVS
    0 references
    timed automata
    0 references
    verification
    0 references

    Identifiers

    0 references
    0 references
    0 references
    0 references
    0 references
    0 references