Approximation scheme for restricted discrete gate sizing targeting delay minimization (Q491218): Difference between revisions

From MaRDI portal
Importer (talk | contribs)
Changed an Item
ReferenceBot (talk | contribs)
Changed an Item
 
(4 intermediate revisions by 4 users not shown)
Property / describes a project that uses
 
Property / describes a project that uses: TILOS / rank
 
Normal rank
Property / MaRDI profile type
 
Property / MaRDI profile type: MaRDI publication profile / rank
 
Normal rank
Property / full work available at URL
 
Property / full work available at URL: https://doi.org/10.1007/s10878-009-9267-0 / rank
 
Normal rank
Property / OpenAlex ID
 
Property / OpenAlex ID: W1980050726 / rank
 
Normal rank
Property / cites work
 
Property / cites work: An improved FPTAS for Restricted Shortest Path. / rank
 
Normal rank
Property / cites work
 
Property / cites work: Approximation Schemes for the Restricted Shortest Path Problem / rank
 
Normal rank
Property / cites work
 
Property / cites work: Chebyshev's approximation algorithms and applications / rank
 
Normal rank
links / mardi / namelinks / mardi / name
 

Latest revision as of 17:05, 10 July 2024

scientific article
Language Label Description Also known as
English
Approximation scheme for restricted discrete gate sizing targeting delay minimization
scientific article

    Statements

    Approximation scheme for restricted discrete gate sizing targeting delay minimization (English)
    0 references
    0 references
    0 references
    24 August 2015
    0 references
    combinatorial optimization
    0 references
    VLSI design
    0 references
    delay optimization
    0 references
    discrete gate sizing
    0 references
    fully polynomial time approximation scheme
    0 references

    Identifiers