Equivalence checking and intersection of deterministic timed finite state machines (Q6108432): Difference between revisions

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+Automata, Languages and Programming
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+Q3601411
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+A theory of timed automata
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+Event-clock automata: a determinizable class of timed automata
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+Formal Methods for the Design of Real-Time Systems
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+Learning One-Clock Timed Automata
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+Q2775857
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+On the power of non-observable actions in timed automata
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+Q4264103
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+Updatable timed automata
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+Undecidability Results for Timed Automata with Silent Transitions
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+Q4995370
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+Formal language properties of hybrid systems with strong resets
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+Testing Software Design Modeled by Finite-State Machines
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+Removing ε-transitions in timed automata
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+Q2708466
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+Removing All Silent Transitions from Timed Automata
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+Distinguishing Experiments for Timed Nondeterministic Finite State Machines
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+Reachability in two-clock timed automata is PSPACE-complete
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+Q3396573
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+Undecidable Problems About Timed Automata
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+A menagerie of timed automata
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+Event Clock Automata: From Theory to Practice
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+Testing from a stochastic timed system with a fault model
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+Switching and Finite Automata Theory
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+CONCUR 2004 - Concurrency Theory
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+Formal testing from timed finite state machines
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+Q4953401
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+Compositional specification of timed systems
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+Testing timed automata
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+On the Verification of Timed Discrete-Event Models
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+Learning Mealy machines with one timer
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+One-Clock Deterministic Timed Automata Are Efficiently Identifiable in the Limit
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+The efficiency of identifying timed automata and the power of clocks
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+The Unknown Component Problem
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+A survey of timed automata for the development of real-time systems
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+Publication:6108432