A single-machine, single-wafer-processing, multiple-lots-per-carrier scheduling problem to minimize the sum of lot completion times (Q1762129): Difference between revisions

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Property / DOI: 10.1016/j.cor.2011.08.012 / rank
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Property / author: Sarin, Subhash C. / rank
 
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Property / describes a project that uses: CPLEX / rank
 
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Property / full work available at URL: https://doi.org/10.1016/j.cor.2011.08.012 / rank
 
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Property / OpenAlex ID: W2033097765 / rank
 
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Property / cites work
 
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Latest revision as of 09:12, 11 December 2024

scientific article
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English
A single-machine, single-wafer-processing, multiple-lots-per-carrier scheduling problem to minimize the sum of lot completion times
scientific article

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    A single-machine, single-wafer-processing, multiple-lots-per-carrier scheduling problem to minimize the sum of lot completion times (English)
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    15 November 2012
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    single machine
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    wafer fabrication
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    multiple-lots-per-carrier
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    single-wafer-processing
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    branch-and-bound
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    completion time
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    \texttt{CPLEX 12.2}
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