A single-machine, single-wafer-processing, multiple-lots-per-carrier scheduling problem to minimize the sum of lot completion times
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Publication:1762129
DOI10.1016/j.cor.2011.08.012zbMath1251.90184OpenAlexW2033097765MaRDI QIDQ1762129
Ming Cheng, Li-Xin Wang, Sarin, Subhash C.
Publication date: 15 November 2012
Published in: Computers \& Operations Research (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.cor.2011.08.012
branch-and-boundsingle machinecompletion timewafer fabrication\texttt{CPLEX 12.2}multiple-lots-per-carriersingle-wafer-processing
Polyhedral combinatorics, branch-and-bound, branch-and-cut (90C57) Deterministic scheduling theory in operations research (90B35)
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