Chai-Tea, Cryptographic Hardware Implementations of xTEA (Q5504636): Difference between revisions

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Normal rank
Property / cites work
 
Property / cites work: Q4484891 / rank
 
Normal rank
Property / cites work
 
Property / cites work: New results on the genetic cryptanalysis of TEA and reduced-round versions of XTEA / rank
 
Normal rank
Property / cites work
 
Property / cites work: Q3046338 / rank
 
Normal rank
Property / cites work
 
Property / cites work: A Regular Layout for Parallel Adders / rank
 
Normal rank
Property / cites work
 
Property / cites work: Cryptographic Hardware and Embedded Systems - CHES 2004 / rank
 
Normal rank
Property / cites work
 
Property / cites work: New Lightweight DES Variants / rank
 
Normal rank
Property / cites work
 
Property / cites work: Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms — Design andAnalysis / rank
 
Normal rank
Property / cites work
 
Property / cites work: PRESENT: An Ultra-Lightweight Block Cipher / rank
 
Normal rank
Property / cites work
 
Property / cites work: AES on FPGA from the Fastest to the Smallest / rank
 
Normal rank
links / mardi / namelinks / mardi / name
 

Latest revision as of 00:30, 29 June 2024

scientific article; zbMATH DE number 5496665
Language Label Description Also known as
English
Chai-Tea, Cryptographic Hardware Implementations of xTEA
scientific article; zbMATH DE number 5496665

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    Chai-Tea, Cryptographic Hardware Implementations of xTEA (English)
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    22 January 2009
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    efficient implementation
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    symmetric key algorithms
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    TEA
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    XTEA
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    FPGA
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    ASIC
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