A compact DSP core with static floating-point arithmetic (Q2432118): Difference between revisions
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| Property / DOI: 10.1007/s11265-005-4178-5 / rank | |||
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| Property / full work available at URL: https://doi.org/10.1007/s11265-005-4178-5 / rank | |||
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| Property / OpenAlex ID: W2170840568 / rank | |||
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| Property / cites work: Q4779782 / rank | |||
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| Property / cites work: Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing / rank | |||
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| Property / cites work: Q4343019 / rank | |||
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| Property / DOI: 10.1007/S11265-005-4178-5 / rank | |||
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Latest revision as of 14:38, 18 December 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A compact DSP core with static floating-point arithmetic |
scientific article |
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A compact DSP core with static floating-point arithmetic (English)
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25 October 2006
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signal processing
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