Parallel VLSI test in a shared-memory multiprocessor (Q2777814): Difference between revisions
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Parallel VLSI test in a shared-memory multiprocessor | |||
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| Property / cites work: An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits / rank | |||
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| Property / cites work: Families of Reed-Muller canonical forms / rank | |||
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| Property / full work available at URL: https://doi.org/10.1002/1096-9128(20000425)12:5<311::aid-cpe492>3.0.co;2-q / rank | |||
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| Property / OpenAlex ID: W2170642360 / rank | |||
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Parallel VLSI test in a shared-memory multiprocessor (English) | |||
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Latest revision as of 11:13, 30 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Parallel VLSI test in a shared-memory multiprocessor |
scientific article |
Statements
7 March 2002
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VLSI test
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distributed-memory multicomputer
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Parallel VLSI test in a shared-memory multiprocessor (English)
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