Parallel VLSI test in a shared-memory multiprocessor

DOI<311::AID-CPE492>3.0.CO;2-Q 10.1002/1096-9128(20000425)12:5<311::AID-CPE492>3.0.CO;2-QzbMath0991.68160OpenAlexW2170642360MaRDI QIDQ2777814

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Publication date: 7 March 2002

Full work available at URL: https://doi.org/10.1002/1096-9128(20000425)12:5<311::aid-cpe492>3.0.co;2-q

zbMATH Keywords

distributed-memory multicomputerVLSI test

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

Related Items (1)

A hybrid meta-heuristic for multi-objective optimization: MOSATS

Cites Work

• Families of Reed-Muller canonical forms
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

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