New lower bound techniques for VLSI (Q3950484): Difference between revisions

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Latest revision as of 10:01, 30 July 2024

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New lower bound techniques for VLSI
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    New lower bound techniques for VLSI (English)
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    1984
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    crossing number
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    wire area
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    layout area
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    maximum edge length
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    N-node planar graph
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    area-efficient chip layouts
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    bisection width
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    graph embedding
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    mesh of trees
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    parallel computation
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    separator
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    Thompson grid model
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    tree of meshes
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    very large scale integration
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    wire length
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