New lower bound techniques for VLSI
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Publication:3950484
DOI10.1007/BF01744433zbMath0488.94048OpenAlexW2066782398MaRDI QIDQ3950484
Publication date: 1984
Published in: Mathematical Systems Theory (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/bf01744433
parallel computationcrossing numbergraph embeddingvery large scale integrationseparatormesh of treesbisection widthlayout areatree of mesheswire lengthThompson grid modelarea-efficient chip layoutsmaximum edge lengthN-node planar graphwire area
Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)
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Cites Work
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- Area-time optimal VLSI networks for multiplying matrices
- The VLSI Complexity of Sorting
- A model of computation for VLSI with related complexity results
- Universality considerations in VLSI circuits
- Applications of a Planar Separator Theorem
- Bounds to Complexities of Networks for Sorting and for Switching
- The crossing number of K5,n
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