The VLSI Complexity of Sorting
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Publication:3036700
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(15)- Improving the average delay of sorting
- Running ASCEND, DESCEND and PIPELINE algorithms in parallel using small processors
- Constant time sorting on a processor array with a reconfigurable bus system
- Functional inversion and communication complexity
- New lower bound techniques for VLSI
- VLSI-sorting evaluated under the linear model
- A minimum-area circuit for \(\ell\)-selection
- Area-time lower-bound techniques with applications to sorting
- A parallel-design distributed-implementation (PDDI) general-purpose computer
- Parallel ear decomposition search (EDS) and st-numbering in graphs
- Finding Euler tours in parallel
- Parallel integer sorting using small operations
- Time lower bounds for parallel sorting on a mesh-connected processor array
- Fault-tolerance VLSI sorters
- The foundation of self-developing blob machines for spatial computing
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