Design constraints for third-order PLL nodes in master-slave clock distribution networks (Q720170): Difference between revisions

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-.1016/j.cnsns.2009.09.039
@@ Property / DOI: 10.1016/j.cnsns.2009.09.039 / rank @@
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+All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus
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+Models for master-slave clock distribution networks with third-order phase-locked loops
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+.1016/J.CNSNS.2009.09.039
@@ Property / DOI: 10.1016/J.CNSNS.2009.09.039 / rank @@
+Normal rank