Implementation of the AES-128 on Virtex-5 FPGAs (Q3506369): Difference between revisions

@@ Property / author @@
-François-Xavier Standaert
@@ Property / author: François-Xavier Standaert / rank @@
-Normal rank
@@ Property / author @@
+François-Xavier Standaert
@@ Property / author: François-Xavier Standaert / rank @@
+Normal rank
@@ Property / MaRDI profile type @@
+MaRDI publication profile
@@ Property / MaRDI profile type: MaRDI publication profile / rank @@
+Normal rank
@@ Property / Wikidata QID @@
+Q58765281
@@ Property / Wikidata QID: Q58765281 / rank @@
+Normal rank
@@ Property / full work available at URL @@
+https://doi.org/10.1007/978-3-540-68164-9_2
+Normal rank
@@ Property / OpenAlex ID @@
+W1698058651
@@ Property / OpenAlex ID: W1698058651 / rank @@
+Normal rank
@@ Property / cites work @@
+Q4797794
@@ Property / cites work: Q4797794 / rank @@
+Normal rank
@@ Property / cites work @@
+AES on FPGA from the Fastest to the Smallest
@@ Property / cites work: AES on FPGA from the Fastest to the Smallest / rank @@
+Normal rank
@@ Property / cites work @@
+A Very Compact S-Box for AES
@@ Property / cites work: A Very Compact S-Box for AES / rank @@
+Normal rank
@@ Property / cites work @@
+Cryptographic Hardware and Embedded Systems - CHES 2004
+Normal rank
@@ Property / cites work @@
+Q4797785
@@ Property / cites work: Q4797785 / rank @@
+Normal rank
@@ Property / cites work @@
+Q4786104
@@ Property / cites work: Q4786104 / rank @@
+Normal rank
@@ links / mardi / name / links / mardi / name @@
+Publication:3506369