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Latest revision as of 13:27, 5 March 2024

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Automatic Verification of Sequential Circuits Using Temporal Logic
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    Automatic Verification of Sequential Circuits Using Temporal Logic (English)
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    1986
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    asynchronous circuits
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    hardware verification
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    correctness of sequential circuits
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    propositional temporal logic
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    state-transition graph
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    truth of a temporal formula
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