Automatic Verification of Sequential Circuits Using Temporal Logic

DOI10.1109/TC.1986.1676711zbMATH Open0604.94011MaRDI QIDQ3743249FDOQ3743249

Authors: M. C. Browne, Bud Mishra, Edmund Clarke, David L. Dill 

Publication date: 1986

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

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zbMATH Keywords

hardware verificationpropositional temporal logicasynchronous circuitscorrectness of sequential circuitsstate-transition graphtruth of a temporal formula

Mathematics Subject Classification ID

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• Symbolic model checking: \(10^{20}\) states and beyond
• Proving sequential function chart programs using timed automata
• Indentification of inductive properties during verification of synchronous sequential circuits
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• CTL\(^*\) and ECTL\(^*\) as fragments of the modal \(\mu\)-calculus
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• Asynchronous logic circuits and sheaf obstructions
• A formalism to describe cyclogram testing models and perform model verification
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• Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic
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• TEMPORAL LOGICS FOR TRACE SYSTEMS: ON AUTOMATED VERIFICATION
• Machine checked proofs of the design of a fault-tolerant circuit
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• Hierarchical verification of asynchronous circuits using temporal logic
• Description and reasoning of VLSI circuit in temporal logic
• Automatic and hierarchical verification for concurrent systems
• A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor
• Automated Technology for Verification and Analysis

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