Automatic and hierarchical verification for concurrent systems

DOI10.1007/BF02945312zbMATH Open0725.68044OpenAlexW2077833819MaRDI QIDQ2277847FDOQ2277847

Authors: Xudong Zhao, Yulin Feng 

Publication date: 1990

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02945312

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zbMATH Keywords

Petri netsbranching time temporal logiccorrectness of concurrent systems

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Cites Work

• Automatic verification of finite-state concurrent systems using temporal logic specifications
• “Sometimes” and “not never” revisited
• Title not available (Why is that?)
• The temporal logic of branching time
• Automatic Verification of Sequential Circuits Using Temporal Logic
• Hierarchical verification of asynchronous circuits using temporal logic

Cited In (12)

• Verifying Concurrent Systems with Symbolic Execution
• Testing Systems of Concurrent Black-Boxes—An Automata-Theoretic and Decompositional Approach
• Automated Verification of Concurrent Search Structures
• Title not available (Why is that?)
• Compositional verification of asynchronous concurrent systems using CADP
• Automatic Verification of Bossa Scheduler Properties
• Interactive verification of concurrent systems using symbolic execution
• Automatic generation of verified concurrent hardware using VHDL
• On the role of automated theorem proving in the compile-time derivation of concurrency
• A formal methodology using attributed grammars for multiprocessing-system software development. II. Validation
• Caper
• Title not available (Why is that?)

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