Asynchronous Logic Circuits and Sheaf Obstructions
From MaRDI portal
Publication:5179025
DOI10.1016/j.entcs.2012.05.010zbMath1337.94114arXiv1008.2729OpenAlexW2078034056WikidataQ113318116 ScholiaQ113318116MaRDI QIDQ5179025
Publication date: 18 March 2015
Published in: Electronic Notes in Theoretical Computer Science (Search for Journal in Brave)
Full work available at URL: https://arxiv.org/abs/1008.2729
Lua error in Module:PublicationMSCList at line 37: attempt to index local 'msc_result' (a nil value).
Related Items (3)
Distributed computation of coverage in sensor networks by homological methods ⋮ A Sheaf-Theoretic Perspective on Sampling ⋮ Political structures and the topology of simplicial complexes
Cites Work
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Compiling communicating processes into delay-insensitive VLSI circuits
- On several geometric aspects of nonlinear networks
- Unicursal resistive networks
- On the mathematical foundations of electrical circuit theory
- Asynchronous operators of sequential logic: Venjunction \& sequention. Digital circuit analysis and design
- AN APPLICATION OF ALGEBRAIC TOPOLOGY TO NUMERICAL ANALYSIS: ON THE EXISTENCE OF A SOLUTION TO THE NETWORK PROBLEM
- Automatic Verification of Sequential Circuits Using Temporal Logic
- A timing refinement of intuitionistic proofs and its application to the timing analysis of combinational circuits
- Logic Synthesis for Asynchronous Controllers and Interfaces
- On the delay-sensitivity of gate networks
This page was built for publication: Asynchronous Logic Circuits and Sheaf Obstructions