Design constraints for third-order PLL nodes in master-slave clock distribution networks (Q720170): Difference between revisions

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Property / DOI: 10.1016/j.cnsns.2009.09.039 / rank
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Property / author
 
Property / author: Átila Madureira Bueno / rank
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Property / author: André Alves Ferreira / rank
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Property / author: Q539728 / rank
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Property / author
 
Property / author: Átila Madureira Bueno / rank
 
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Property / author
 
Property / author: André Alves Ferreira / rank
 
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Property / author
 
Property / author: José Roberto Castilho Piqueira / rank
 
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Property / MaRDI profile type: MaRDI publication profile / rank
 
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Property / full work available at URL: https://doi.org/10.1016/j.cnsns.2009.09.039 / rank
 
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Property / OpenAlex ID: W2092361954 / rank
 
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Property / cites work
 
Property / cites work: All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus / rank
 
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Property / cites work
 
Property / cites work: Models for master-slave clock distribution networks with third-order phase-locked loops / rank
 
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Property / cites work
 
Property / cites work: Fast projection methods for minimal design problems in linear system theory / rank
 
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Property / cites work: Nonlinear oscillations, dynamical systems, and bifurcations of vector fields / rank
 
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Property / cites work: Q3157814 / rank
 
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Property / cites work: Q4692840 / rank
 
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Property / cites work: Nonlinear control systems: An introduction / rank
 
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Property / DOI
 
Property / DOI: 10.1016/J.CNSNS.2009.09.039 / rank
 
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Latest revision as of 01:47, 10 December 2024

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Design constraints for third-order PLL nodes in master-slave clock distribution networks
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