Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach (Q4015507): Difference between revisions
From MaRDI portal
Added link to MaRDI item. |
Set profile property. |
||
| Property / MaRDI profile type | |||
| Property / MaRDI profile type: MaRDI publication profile / rank | |||
Normal rank | |||
Latest revision as of 13:49, 5 March 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach |
scientific article |
Statements
Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach (English)
0 references
13 January 1993
0 references
combinatorial optimization
0 references
gate matrix layout
0 references
consecutive ones property
0 references
VLSI design
0 references
heuristic algorithms
0 references
PLA folding
0 references
matrix layout problem
0 references
complexity
0 references
