Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (Q305062): Difference between revisions
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Latest revision as of 11:13, 12 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers |
scientific article |
Statements
Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (English)
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26 August 2016
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computer arithmetic
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binary-coded decimal
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BCD digit multipliers
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binary-to-BCD converters
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decimal VLSI-friendly array multipliers
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combinational logic
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