Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

DOI10.1007/S00034-014-9823-4zbMath1344.68019OpenAlexW2042543662MaRDI QIDQ305062

Ghassem Jaberipur, Saeid Gorgin, Reza Hashemi Asl

Publication date: 26 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-014-9823-4

zbMATH Keywords

BCD digit multipliersbinary-coded decimalbinary-to-BCD converterscombinational logiccomputer arithmeticdecimal VLSI-friendly array multipliers

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Uses Software

• dfp

Cites Work

• Structural damage detection using an efficient correlation-based index and a modified genetic algorithm
• A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
• Improving the Speed of Parallel Decimal Multiplication
• Improved Design of High-Performance Parallel Decimal Multipliers
• High-Speed Binary-to-Decimal Conversion
• Serial Binary-to-Decimal and Decimal-to-Binary Conversion
• Iterative Arrays ror Radix Conversion

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