Ghassem Jaberipur

Available identifiers

Publication	Date of Publication	Type
Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems with Fast 16-bit Residue Channels	2022-08-05	Paper
https://portal.mardi4nfdi.de/entity/Q5008354	2021-08-26	Paper
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems	2017-11-20	Paper
Improving the Speed of Parallel Decimal Multiplication	2017-08-08	Paper
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value	2017-07-27	Paper
Decimal square root: algorithm and hardware implementation	2017-07-10	Paper
Comment on “High Speed Parallel Decimal Multiplication With Redundant Internal Encodings”	2017-05-16	Paper
Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers	2016-08-26	Paper
An improved maximally redundant signed digit adder	2010-05-27	Paper
A Nonspeculative Maximally Redundant Signed Digit Adder	2009-05-20	Paper
An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding	2006-10-25	Paper
https://portal.mardi4nfdi.de/entity/Q5719012	2006-01-16	Paper

This page was built for person: Ghassem Jaberipur