Ghassem Jaberipur

List of research outcomes

This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon!

Publication	Date of Publication	Type
Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems with Fast 16-bit Residue Channels IEEE Transactions on Computers	2022-08-05	Paper
scientific article; zbMATH DE number 7385997 (Why is no real title available?)	2021-08-26	Paper
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems IEEE Transactions on Circuits and Systems I: Regular Papers	2017-11-20	Paper
Improving the Speed of Parallel Decimal Multiplication IEEE Transactions on Computers	2017-08-08	Paper
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value IEEE Transactions on Computers	2017-07-27	Paper
Decimal square root: algorithm and hardware implementation Circuits, Systems, and Signal Processing	2017-07-10	Paper
Comment on “High Speed Parallel Decimal Multiplication With Redundant Internal Encodings” IEEE Transactions on Computers	2017-05-16	Paper
Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers Circuits, Systems, and Signal Processing	2016-08-26	Paper
An improved maximally redundant signed digit adder Computers and Electrical Engineering	2010-05-27	Paper
A Nonspeculative Maximally Redundant Signed Digit Adder Communications in Computer and Information Science	2009-05-20	Paper
An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding Journal of VLSI signal processing systems for signal, image and video technology	2006-10-25	Paper
scientific article; zbMATH DE number 2247814 (Why is no real title available?)	2006-01-16	Paper

Research outcomes over time

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