Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

DOI10.1007/S00034-014-9823-4MaRDI QIDQ305062zbMATH OpenOpenAlexFDO

Authors Saeid Gorgin, Ghassem Jaberipur, Reza Hashemi Asl

Publication date 26 August 2016

Published in Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s00034-014-9823-4

zbMATH Keywords

BCD digit multipliersbinary-coded decimalbinary-to-BCD converterscombinational logiccomputer arithmeticdecimal VLSI-friendly array multipliers

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cites work

• A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
• High-Speed Binary-to-Decimal Conversion
• Improved Design of High-Performance Parallel Decimal Multipliers
• Improving the Speed of Parallel Decimal Multiplication
• Iterative Arrays ror Radix Conversion
• Serial Binary-to-Decimal and Decimal-to-Binary Conversion
• Structural damage detection using an efficient correlation-based index and a modified genetic algorithm

Cited in

(5)

• Fast Radix-10 Multiplication Using Redundant BCD Codes
• Area-Efficient Multipliers Based on Multiple-Radix Representations
• Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
• Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials
• Improved Design of High-Performance Parallel Decimal Multipliers

Describes a project that uses

Uses Software

• dfp

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