Area-Efficient Multipliers Based on Multiple-Radix Representations

DOI10.1109/TC.2010.200zbMATH Open1367.65214OpenAlexW1971540551MaRDI QIDQ5280628FDOQ5280628

Authors: Kimmo Järvinen, Jithra Adikari, Vassil S. Dimitrov 

Publication date: 27 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2010.200

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Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited In (6)

• Area—Time optimal VLSI integer multiplier with minimum computation time
• Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers
• Title not available (Why is that?)
• A Low-Complexity High-Radix RNS Multiplier
• Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
• Fast Radix-10 Multiplication Using Redundant BCD Codes

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