Method for designing efficient mixed radix multipliers

DOI10.1007/s00034-014-9799-0zbMath1342.68034OpenAlexW2028836842MaRDI QIDQ531246

H. Pettenghi, F. Pratas, Leonel Sousa

Publication date: 3 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-014-9799-0

zbMATH Keywords

residue number systemvery large scale integration (VLSI) designBooth multiplierscomputer arithmeticsmodulo arithmetic

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Cites Work

• Unnamed Item
• A simplified architecture for module (2/sup n/+1) multiplication
• A universal architecture for designing efficient modulo 2/sup n/+1 multipliers
• Area-Power Efficient Modulo $2^{n}-1$ and Modulo $2^{n}+1$ Multipliers for $\{2^{n}-1, 2^{n}, 2^{n}+1\}$ Based RNS
• Radix-8 Booth Encoded Modulo $2 ^{n} -1$ Multipliers With Adaptive Delay for High Dynamic Range Residue Number System
• A SIGNED BINARY MULTIPLICATION TECHNIQUE

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