Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers

DOI10.1007/s40010-021-00745-wzbMath1497.94195OpenAlexW3155973371MaRDI QIDQ2676842

Gholamreza Zare Fatin, Ali Rahnamaei

Publication date: 28 September 2022

Published in: Proceedings of the National Academy of Sciences, India. Section A. Physical Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s40010-021-00745-w

zbMATH Keywords

radix-4high-speedparallel multiplierBooth algorithmBooth encoding schemepass-transistor logic

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Cites Work

• Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
• Optimal circuits for parallel multipliers
• Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
• Radix-8 Booth Encoded Modulo $2 ^{n} -1$ Multipliers With Adaptive Delay for High Dynamic Range Residue Number System
• A Reduced Complexity Wallace Multiplier Reduction
• Majority Gate Networks
• A SIGNED BINARY MULTIPLICATION TECHNIQUE

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