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swMATH5671MaRDI QIDQ17810FDOQ17810
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Cited In (5)
- A study of decimal left shifters for binary numbers
- Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers
- Mathematical model and implementation of rational processing
- An iterative method for improving decimal calculations on computers
- MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
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