Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (Q305062)
From MaRDI portal
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers |
scientific article |
Statements
Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (English)
0 references
26 August 2016
0 references
computer arithmetic
0 references
binary-coded decimal
0 references
BCD digit multipliers
0 references
binary-to-BCD converters
0 references
decimal VLSI-friendly array multipliers
0 references
combinational logic
0 references
0 references
