Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (Q305062)
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scientific article; zbMATH DE number 6619939
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| English | Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers |
scientific article; zbMATH DE number 6619939 |
Statements
Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (English)
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26 August 2016
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computer arithmetic
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binary-coded decimal
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BCD digit multipliers
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binary-to-BCD converters
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decimal VLSI-friendly array multipliers
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combinational logic
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0.7085522413253784
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0.6853905916213989
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