Improving the Speed of Parallel Decimal Multiplication

DOI10.1109/TC.2009.110MaRDI QIDQ4974883zbMATH OpenOpenAlexFDO

Authors Ghassem Jaberipur, Amir Kaivani

Publication date 8 August 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2009.110

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited in

(6)

• SPEEDING UP MULTI- EXPONENTIATION ALGORITHM ON A MULTICORE SYSTEM
• Parallel implementation of multiple-precision arithmetic and 2,576,980,370,000 decimal digits of calculation
• Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers
• Improved Design of High-Performance Parallel Decimal Multipliers
• An iterative method for improving decimal calculations on computers
• scientific article; zbMATH DE number 3223196 (Why is no real title available?)

This page was built for publication: Improving the Speed of Parallel Decimal Multiplication

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4974883)