Q4040310 (Q4040310): Difference between revisions
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scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | No label defined |
scientific article |
Statements
5 June 1993
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design of VLSI circuits
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simulated annealing
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combinatorial optimization
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placement
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floorplan design
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channel routing
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Programmable Logic Array folding
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Gate Matrix layout
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logic array optimization
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design automation
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