scientific article; zbMATH DE number 193510

MaRDI QIDQ4040310zbMATH OpenFDO

Authors

Publication date 5 June 1993

zbMATH Keywords

channel routingcombinatorial optimizationdesign automationdesign of VLSI circuitsfloorplan designGate Matrix layoutlogic array optimizationplacementProgrammable Logic Array foldingsimulated annealing

Mathematics Subject Classification ID

Circuits, networks (94C99)

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(20)

• Guillotineable bin packing: A genetic approach
• A simulated annealing channel routing algorithm
• Global optimization by multilevel search
• Placement by thermodynamic simulated annealing
• Application of the simulated annealing local search technique to problems of redundancy elimination in functional and parametric tests of integrated circuits
• Review on nature-inspired algorithms
• The designs of S-boxes by simulated annealing
• Mixing time and simulated annealing for the stochastic cellular automata
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• Global optimization of statistical functions with simulated annealing
• Mathematical aspects of the Digital Annealer's simulated annealing algorithm
• Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem
• Mathematical methods for physical layout of printed circuit boards: an overview

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