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This interesting research monograph covers topics in the design of VLSI circuits using the method of simulated annealing. The method of simulated annealing is an adaption of the procedure of iterative improvement based on an analogy between a combinatorial optimization problem of determining the lowest-energy ground state of a system. In chapter 1 a brief discussion of the method of simulated annealing and combinatorial optimization is given. In the other seven chapters the authors treat simulated annealing based algorithms for various design aspects of VLSI circuits. In particular, the authors discuss algorithms for placement, floorplan design, channel routing (two chapters), Programmable Logic Array folding, Gate Matrix layout and logic array optimization. Individuals interested in design automation and, in particular, VLSI design will find this monograph a useful source of information on the application of the simulated annealing method.