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scientific article; zbMATH DE number 193510
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| default for all languages | No label defined |
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| English | No label defined |
scientific article; zbMATH DE number 193510 |
Statements
5 June 1993
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design of VLSI circuits
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simulated annealing
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combinatorial optimization
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placement
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floorplan design
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channel routing
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Programmable Logic Array folding
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Gate Matrix layout
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logic array optimization
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design automation
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0.90389514
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