Technology mapping and placement for delay-minimization in LUT-based FPGA design (Q1288423): Difference between revisions
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Revision as of 06:15, 29 February 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Technology mapping and placement for delay-minimization in LUT-based FPGA design |
scientific article |
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Technology mapping and placement for delay-minimization in LUT-based FPGA design (English)
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11 May 1999
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FPGA
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minimum delay mapped circuit
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