A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (Q1208500): Difference between revisions
From MaRDI portal
Added link to MaRDI item. |
Set profile property. |
||
| Property / MaRDI profile type | |||
| Property / MaRDI profile type: MaRDI publication profile / rank | |||
Normal rank | |||
Latest revision as of 03:32, 5 March 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A methodology for algorithm regularization and mapping into time-optimal VLSI arrays |
scientific article |
Statements
A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (English)
0 references
16 May 1993
0 references
systolic precedence diagram
0 references
systolic directed graph
0 references
graph methodology for regularizing data flow
0 references
algorithmic transformations
0 references
systolic architecture
0 references
mapping
0 references
systolic implementation
0 references
time-optimal VLSI arrays
0 references
