Timed verification of the generic architecture of a memory circuit using parametric timed automata (Q1028737): Difference between revisions
From MaRDI portal
Set OpenAlex properties. |
ReferenceBot (talk | contribs) Changed an Item |
||
Property / cites work | |||
Property / cites work: A theory of timed automata / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Verification of Asynchronous Circuits using Timed Automata / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Static Analysis / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Uppaal in a nutshell / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Formal Modeling and Analysis of Timed Systems / rank | |||
Normal rank | |||
Property / cites work | |||
Property / cites work: Kronos: A verification tool for real-time systems / rank | |||
Normal rank |
Latest revision as of 18:56, 1 July 2024
scientific article
Language | Label | Description | Also known as |
---|---|---|---|
English | Timed verification of the generic architecture of a memory circuit using parametric timed automata |
scientific article |
Statements
Timed verification of the generic architecture of a memory circuit using parametric timed automata (English)
0 references
6 July 2009
0 references
memory circuit
0 references
timed automata
0 references
model checking
0 references
0 references