Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata (Q3511227)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata |
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Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata (English)
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8 July 2008
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