Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata (Q3511227)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 5299126
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata |
scientific article; zbMATH DE number 5299126 |
Statements
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata (English)
0 references
8 July 2008
0 references
0.9605494737625122
0 references
0.7845503091812134
0 references
0.7522932887077332
0 references
