Design constraints for third-order PLL nodes in master-slave clock distribution networks (Q720170): Difference between revisions
From MaRDI portal
ReferenceBot (talk | contribs) Changed an Item |
Normalize DOI. |
||
| Property / DOI | |||
| Property / DOI: 10.1016/j.cnsns.2009.09.039 / rank | |||
| Property / DOI | |||
| Property / DOI: 10.1016/J.CNSNS.2009.09.039 / rank | |||
Normal rank | |||
Revision as of 08:06, 9 December 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Design constraints for third-order PLL nodes in master-slave clock distribution networks |
scientific article |
Statements
Design constraints for third-order PLL nodes in master-slave clock distribution networks (English)
0 references
13 October 2011
0 references
phase-locked loop
0 references
second-order filter
0 references
synchronization
0 references
stability
0 references
0 references
